The present invention relates to a semiconductor memory device including a plurality of memory cells each of which is formed of MOS (metal oxide semiconductor) transistors, and more particularly to a semiconductor memory device with an improved means for reading data from the memory cells.
An arrangement of a memory cell for constituting a prior art memory device is illustrated in FIG. 1 with its peripheral circuit. Although only a single memory cell is illustrated in the figure, a number of memory cells are actually arranged in a matrix fashion to form a memory device. As shown in FIG. 1, the memory cell 1 includes a first series circuit of a load resistor 2 and an MOS transistor 4, a second series circuit of a load resistor 3 and an MOS transistor 5, each of which being connected between a first power source V.sub.DD and a second power source V.sub.SS (earth potential); an MOS transistor 6 serving as a first transfer gate which is connected between a bit line 9 and a connection point of the load resistor 2 to the MOS transistor 4; and an MOS transistor 7 serving as a second transfer gate which is connected between a bit line 10 and a connection point of the load resistor 3 to the MOS transistor 5.
A word line 8 is connected to the gate electrodes of the MOS transistors 6 and 7. Precharge MOS transistors 11 and 12 are connected between the first power source V.sub.DD and the bit line 9 and between the first power source V.sub.DD and the bit line 10, respectively. The gate electrodes of these MOS transistors 11, 12 are kept at the potential of the second power source V.sub.SS. Connected between the bit lines 9 and 10 is a sense amplifier 13 for sensing the data stored in the memory cell 1 in the form of a potential difference between the bit lines 9 and 10. The output signal from the sense amplifier 13 is applied to a main amplifier 16 through MOS transistors 14 and 15 serving as transfer gates. The main amplifier 16 serves to produce the data DA. Reference numeral 18 designates a column selection signal. Reference numerals 19 and 20 designate stray capacitances of the bit lines 9 and 10, respectively. The gate electrode of the MOS transistor 5 is connected to a connection point between the resistor 2 and the MOS transistor 4. The gate electrode of the MOS transistor 4 is connected to a connection point between the resistor 3 and MOS transistor 5.
In FIG. 1, when the word line 8 is selectively driven, the MOS transistors 6 and 7 are conductive. A pair of the bit lines 9 and 10 have been charged up to the potential of the first power source V.sub.DD, by way of the precharge transistors 11 and 12. Therefore, when the word line 8 is driven, if the MOS transistor 4 is in an ON state and the MOS transistor 5 is in an OFF state, a current (DC) flows through a route (or current path) including the first power source V.sub.DD, the bit line 9, the MOS transistor 6, the MOS transistor 4, and the second power source V.sub.SS (generally kept at an earth potential). As a result of the current flow, a potential difference appears between the bit lines 9 and 10. The potential difference is sensed by the sense amplifier 13. The sensed signal is applied to the main amplifier 16 through the transistors 14 and 15 which are ON-OFF controlled by the column selection signal 18. The data DA (corresponding to the ON state of the MOS transistor 4) stored in the memory cell is produced from the amplifier 16.
When a memory device of N bits is constituted by arranging memory cells shown in FIG. 1 in a matrix fashion, .sqroot.N memory cells are connected to the word line 8. Accordingly, when the data is read out from the memory cell 1 shown in FIG. 1 by selectively driving the word line 8, the DC current also flows through all the non-selected memory cells connected to the word line and belonging to non-selected columns. This DC current flows through the above current path during the time period in which the row selection signal applied to the word line 8 is kept at a second level (high level). This time period is called a one-cycle period of an address signal. The row selection signal is changed to the second level for turning the transistors 6, 7 ON from a first level for turning the transistors 6, 7 OFF. The relationship between the one-cycle time period of the address signal ADR and the current I flowing through the current path is illustrated in FIGS. 2A and 2B. As seen from the figures, the current I slightly increases at time points T.sub.0 and T.sub.0 ' where the address signal ADR changes in level and is kept constant over the one-cycle time period. As seen from FIGS. 2A and 2B, in the prior memory device shown in FIG. 1, the current consumption in the memory device is extremely large because of the presence of the DC current flowing through the memory cell when the data is read out.
Making the conductance of the MOS transistors 11 and 12 small is one of the methods of reducing the current I. If this method is employed, the potential on the bit lines 9 and 10 is reduced to close to the earth potential. When the level drops to such a potential, two word lines are influenced by the capacitances 19 and 20 when the address signal ADR changes its level, and are high at the level changing time point T.sub.0. A so called multi-access state occurs at this time point. In this multi-access state, the data in the memory cell is liable to be destroyed. Further, when the conductances of the MOS transistors 11 and 12 are decreased, the charge time for the bit lines 9 and 10 is increased and the data read speed is damaged.